1. Field of the Invention
The invention relates to methods and apparatus used in systems for communicating data (e.g., voice, video and alphanumeric data), including but not limited to telecommunications systems, computer systems, etc. More particularly, the invention relates to methods and apparatus used to switch telephony and data signals without wasting bandwidth and without compromising the quality of telephony.
2. Brief Description of the Prior Art
Telephony switching was originally based on a system known as time division multiplexing (TDM). Although the actual implementation of TDM is quite complex, the concept of TDM is easy to understand.
Several relatively low frequency signals are interleaved to form a single relatively high frequency signal. The signals are mapped into what is referred to as a frame. Individual telephone connections are assigned a slot in the frame. Each slot corresponds to a destination (or a switch connection).
By nature, TDM provides a constant bandwidth allocation to each telephone connection. Although originally designed for telephony, TDM is also used in data switching. However, when used for data switching, TDM is inefficient. Bandwidth is wasted because most data communication does not require constant bandwidth.
Efficient data switching was initially provided through the use of packets. Packet switching techniques require an arbitration system whereby bandwidth is arbitrated among users. Some packet switching techniques utilize fixed length packets and some use variable length packets. Switch connections (or packet destinations) are specified in a part of the packet called the header.
Packet switching allows for the dynamic allocation of bandwidth to wherever it is needed and allows for xe2x80x9cburstyxe2x80x9d traffic, i.e. traffic which requires a large amount of bandwidth for a short amount of time and then requires little bandwidth.
As the popularity of data communication has spread, many different methods have been proposed for integrating telephony and data. Some of these proposals include ISDN (Integrated Services Digital Network), voice over ATM (Asynchronous Transfer Mode), ATM over SONET (Synchronous optical Network), and voice over IP (Internet Protocol).
The challenge in each of these proposals is to fairly allocate bandwidth without wasting bandwidth, while maintaining quality of service. However, each of these proposals is ultimately based on either TDM (ISDN and SONET) or packet switching (ATM and IP).
Those based on TDM continue to waste bandwidth and those based on packet switching provide poor quality of service during periods of congestion.
In conjunction with the methods proposed for integrating telephony and data, different apparatus have been developed. Although TDM traffic can be packetized and packet traffic can be provisioned over a TDM connection, different switches must be used for each type of traffic.
All digital electronic communication consists of payload data and control data. The payload data can not be readily distinguished from noise without some type of control information by which to interpret it.
To better appreciate the background of the invention it should be understood that there are two types of control information: element synchronization and transmission source synchronization.
Element synchronization provides a means of delineating the logical elements of the data stream, so bits, bytes, frames, etc. can be delineated. Transmission source synchronization, on the other hand, is necessary where more than one source can be simultaneously using the same transmission medium. The sources must be synchronized in time. If two sources attempt to send different data at the same time, the resulting ambiguity renders the data useless.
Both types of control information can be supplied in many forms, from a very simple time synchronization format built into the data stream, as exemplified by the RS-232 serial protocol, to a completely separate stream of data, complex in its own right, as in the PCI bus architecture.
Element synchronization can be achieved by one or more clock signals or by built-in (or on-line) timing.
An example of built-in timing is the RS-232 serial data signal. The RS-232 serial stream, like most digital data, is composed of bits and bytes. A bit can be either logical one or zero; it can have no other value. This can be represented electrically by two voltage levels, two frequencies, presence or absence of a voltage, etc. Eight bits compose a byte. Most digital data is composed of strings of bytes.
An RS-232 stream delineates the beginning of each byte of data by a rise of voltage to a predetermined MARK level (the START bit), followed by eight bits, each being present for a certain length of time, and terminated by a STOP bit of a certain length. This element synchronization makes it possible to extract the intelligence from the data stream by taking samples of the line voltage at periodic intervals following the leading edge of the START bit. This sampling interval is determined by the baud rate of the transmitting device. There is no need to provide a separate clock signal to mark the individual bits.
In contrast, in the PCI bus architecture, discrete time periods are marked off by a separate CLOCK signal. The timing of the clock pulses allows the receiving station to discern the individual bits and bytes of the stream of data on the data transmission bus. In a parallel bus architecture of this type, multiple channels carry data simultaneously, with the bit timing of all channels synchronized to the same external clock.
Transmission source synchronization mechanisms can also be either built-in (xe2x80x9cin bandxe2x80x9d) or external (xe2x80x9cout of bandxe2x80x9d). As mentioned above, if more than one source transmits data into the medium at the same time, unless the data is exactly the same for all sources, the result will be useless noise. Therefore, some of the resources used in the data transmission process must be used for controlling the flow of data.
In other words, there must be some way to determine who can transmit at any particular time.
Resources that are used only for the control of the data flow are referred to as xe2x80x9coverheadxe2x80x9d. These resources are of no value to the ultimate users of the system other than as conveyors of the payload data. The source synchronization overhead, necessary to prevent or compensate for simultaneous transmission by more than one device, can become a significant portion of the available bandwidth; that is, the overall data carrying capacity of a particular transmission medium, such as a fiber optic link or a radio transmission frequency spectrum. Although necessary, the synchronization control overhead is not desirable, since the overhead contributes to the expense of the system.
In some transmission systems, the bandwidth is divided into channels, wherein the data is carried in several parallel xe2x80x9cpipesxe2x80x9d. Parallel means that the data is carried simultaneously in all channels.
In other system, data is carried in a single xe2x80x9cpipexe2x80x9d, in which only one basic element (xe2x80x9cbitxe2x80x9d) is transmitted at a time.
When the medium used carries only a single bit at a time, as in a high-speed serial system (e.g. Ethernet), source synchronization involving several originating sources is a serious problem. If several sources begin transmitting messages at the same time, no other station in the system knows where the message is originating.
In addition, the data of the various transmitting sources is combined in a completely random fashion so that all intelligence is lost. Of necessity, a system of this type must build the source synchronization mechanism into the transmission protocol because there is no external method of controlling access.
The controls for source synchronization that are built-in involve either some method of rotating control of the medium to each source or, alternatively, some method of seizing control of the medium without interfering with or being interfered with by another source.
The former method is embodied in a token ring system, in which a logical xe2x80x9ctokenxe2x80x9d is passed around and only the source possessing the token is allowed to transmit. This method requires that some of the available bandwidth be dedicated to the token handling process.
In the latter method, exemplified by Ethernet, each transmitting source monitors the medium for activity before attempting to transmit. When the source determines that activity has ceased, it begins transmitting.
A collision can occur when two sources attempt to start transmitting at the same time. The two sources must be able to detect the collision and then xe2x80x9cback offxe2x80x9d from the medium for a period of time before retrying. As traffic on the medium increases, the incidence of collisions increases dramatically, causing an effective loss of bandwidth.
External controls refers to an architecture in which the controls for transmission source synchronization are provided by a signal or signals that are in some way separate from the signals that provide the data that is to be transferred (xe2x80x9cout of bandxe2x80x9d). Two examples, described in more detail below, are the PCI bus and a TDM bus. In both of these bus systems, the control signals are distinguished from the data signals by being on different channels. The main advantage of this type of architecture is that little or none of the data bandwidth is expended for control. The disadvantage is the cost of the additional hardware required.
The PCI bus architecture is typical of parallel bus architectures in which more than one source is capable of transmitting simultaneously on the same bus. It employs a source synchronization mechanism to prevent collisions and a clock signal to delineate the bit periods. The source synchronization signals are carried on a physically different set of signal traces from those which carry the data. These control signals provide a means for an arbiter to communicate with contending sources. The arbiter determines which source will have access to the data bus when the bus becomes available and gives that source permission to transmit at that time.
A Time Division Multiplexed architecture in its broader sense is, as indicated hereinbefore, a system that divides data bandwidth into discrete time segments, or xe2x80x9cslotsxe2x80x9d, which are allocated for use by the transmitting sources. The meaning or value of the data is determined by its relative temporal position as measured by element control signals which include a bit clock and a frame clock.
The slots of time within the frame are allocated to the various sources as needed.
In summary, control signals add complexity to the transmission medium architecture, resulting in increased bandwidth requirements or additional investment in hardware, or both. These control signals are carried either on the transmission medium itself or a supplementary medium, or both. Heretofore the only apparent solutions were either over-building bandwidth capacity for a given amount of payload data or investing a significant amount in supplementary hardware and control software.
It is therefore an object of the invention to provide methods and apparatus for performing telephony and data communication more efficiently.
More particularly, it is an object of the invention to provide methods and apparatus for more efficiently utilizing bandwidth in telephony, data communications and combined telephony/data communications applications.
It is a further object of the invention to provide a communications bus that accommodates a plurality of users and arbitrates control of the bus quickly and efficiently.
It is another object of the invention to provide methods and apparatus for telephony, data communications and combined telephony/data communications applications which maintains the quality of service while fairly allocating bandwidth.
It is still another object of the invention to provide methods and apparatus for telephony, data communications and combined telephony/data communications applications in which there is no possibility of data collisions.
It is yet another object of the invention to provide methods and apparatus for the aforementioned applications which do reduce bus management overhead when compared with traditional parallel bus management techniques.
It is another object of the invention to provide methods and apparatus for the aforementioned application which are flexible and easily expandable.
In accord with these objects which will be discussed in detail below, the methods and apparatus for combined telephony and data communication of the present invention include a parallel bus of, preferably, 64 data bits, one clock bit, one bid/busy bit, and one acknowledge (ack) bit.
The invention further includes a plurality, preferably 64, port (xe2x80x9cbus userxe2x80x9d) devices coupled to the bus. Each port device includes bus interface circuitry, port control circuitry, and line interface circuitry. The bus interface circuitry includes input and output FIFOs and control logic. The port control circuitry includes a processor and RAM. The line interface circuitry includes an input line receiver and deserializer and an output line driver and serializer.
The control logic in the bus interface of the circuitry (the preferred embodiment of the invention being described herein) includes 66 line drivers for driving the 64 data lines, the bid/busy line, and the ack line; and 67 line receivers for receiving all of the lines including the clock line.
According to the presently preferred embodiment, each line is pulled up to VCC by a resistor so that a non-driven line is at VCC. The clock signal is used to synchronize messages on the bus and to divide the time domain into timeslots (one timeslot being the reciprocal of the clock frequency).
According to the invention, no frame reference is used and traffic on the bus is controlled using a protocol.
Further, according to the preferred embodiment of the invention, data being received from the bus is stored in the input FIFO automatically, clocked in at a rate equal to the bus clock frequency. Data is transmitted onto the bus at the clock rate, preferably 20 megahertz, giving a total transmit rate of 1.2 gigabits per second.
The protocol of the bus is essential for the most efficient use of the bandwidth. All messages have a common format which complements the rules of protocol. The rules of protocol are:
(1) All ports have an assigned address which correlates to one of the data lines of the bus, i.e. 0-63 in the presently preferred embodiment.
(2) The value of the address is directly related to the priority of the port, e.g. 1 has priority over 2.
(3) No port that has not seized the bus can transmit on the bus if the BID/BUSY line is low (asserted).
(4) All data packets must be at least two clock cycles in length (to achieve maximum efficiency).
(5) A port of fewer than 64 bits will not see a bid by a port with an address that falls out of the range of its receive bus. The port with the higher number of receive/transmit bits, however, will be able to see the other""s bid and cease attempting to seize the bus.
(6) All ports must respect the priority scale in the bid process.
(7) All ports must respect the current state of the BID/BUSY line and maintain a high impedance output on the data bus lines until the transmitting source releases the BID/BUSY line.
When the BID/BUSY line is allowed to go HIGH (inactive), any port can attempt to seize control of the bus on any succeeding cycle so long as no other port seizes control. If a port wishes to seize control of the bus, it must xe2x80x9cbidxe2x80x9d by placing a low on the data line that corresponds to its address (0-63) for one clock cycle at the beginning of the next clock cycle and place a LOW on the BID/BUSY line simultaneously. During the clock cycle in which the port is xe2x80x9cbiddingxe2x80x9d it must sense the other data lines for the presence of bids by other ports. If two ports bid simultaneously, the port with the higher priority address obtains control. Priority is directly related to the binary value of the data line, 0 being the highest priority.
Additionally, according to one embodiment of the invention, ports having fewer data bits than the width of the bus are assigned higher priority than the ports having full data width. For example, using a 64 bit data bus, ports coupled to 5 data lines would have a priority greater that ports connected to 10 data line; ports connected to 10 data lines would have priority greater ports connected to 50 data lines, etc. Within each grouping (10 bit ports, 50 bit ports, etc.), address would control priority.
During the clock cycle following bidding, the controlling port asserts the bus line(s) corresponding to the address(es) of the destination ports. If a port reads its own address during this clock, it asserts the ACK line during the next clock cycle and then immediately release it.
The transmitting port keeps asserting the BID/BUSY line during the entire transmission of the message. The transmitting port releases the BID/BUSY line at the end of the third clock cycle if the ACK line does not go LOW during the third time slot. The BID/BUSY line goes HIGH at the end of the clock cycle during which the last byte is transmitted. The transition of the BID/BUSY voltage to HIGH signals the receiving port that the data packet is complete. It also signals other ports that the bus is now available for bid.
According to the invention, the ports coupled to the bus are similar to the line modules of a TDM based exchange in that they accept analog lines and convert the analog signals into digital data according to the usual PCM encoding rules. The digital data is collected into packets of a suitable length (100 bytes for conversational voice) and transmitted across the bus to one or more ports where it is re-transmitted along the associated link in the appropriate form. Non-voice data is transmitted across the bus without alteration. An important characteristic of all voice line modules is that they search for voice packets containing silence and discard them eliminating the unnecessary use of bus bandwidth.
During the third clock cycle, in addition to asserting the lines described above, the source transmits a byte indicating the type of data to be transmitted.
The switch according to the invention performs the call processing in any one of three ways:
(1) A dedicated port on the bus is notified by another port that call processing services are required.
The dedicated port generates the necessary tones or D-channel messages to establish the call, using data from the notifying port.
(2) The port, itself, has the capability of performing the call process function. This will more usually be the case when the port is a Digital Subscriber Line Integrated Circuit (DSLIC).
(3) The call processing is performed by an external processor attached to the bus via a dedicated port.
The methods and apparatus of the invention actually become more efficient as usage increases. Because the addressing protocol of the invention is efficient, ports govern themselves with respect to bus access and there is no contention for control when a port has relinquished use of the bus. Bidding is done in a controlled manner, with the port having the highest priority allowed to use the bus whenever two or more ports bid for access. Ports can be configured to handle any kind of traffic from POTS (plain old telephone service) to broadband data service.
The bus protocol imposes very little overhead on the packet traffic. The bus can be designed as a relatively inexpensive backbone capable of accepting a large number of ports. The basic configuration can be implemented relatively inexpensively. Expansion is modular, with processing being added with each new module in the exact amount required. The basic design is stackable, by adding connecting buffer ports between adjacent units. Priority of bus use is automatic. The bus is so designed that ports of less than 64 bits can operate on the bus without conflict.
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.